Timing cycles diagram can be defined as the pictorial representation of the execution time taken by each representation in a graphical format. The execution time of any processors  are represented in T- states. Just like heartbeat is required to keep human beings alive, the CLK  is required to keep microprocessor alive, i.e. CLK is required for the proper operation of different sections of the microprocessors.

For example : If a person is asked to bring 8- bags of entities ,each weighing 50 kg , it varies from person to person ability to carry the bag . A person with stronger physical health will perform this task in 4- times only , while a weaker person can perform the same task in 8- times . Let us assume both weaker and stronger person as machine there.

The same thing happens with processor also. A processor can execute a instruction in 3- machine cycles while the other processor can execute it in one- machine cycle also. So it depends on the capability of the processor that how fast (or how many states are required for the execution of the particular instruction) .

The timing diagram of a microprocessor consists of machine cycles and instruction cycles and T-states which are described as follows:

Machine cycle :

The time required to access the memory or input/output devices is called machine cycle. In a usual manner machine cycle consists of 3 to 6 T-states.

Instruction Cycle :

The time required  to execute an instruction is called an instruction cycle .

T- State :

An amount of an operation carried out in one system clock period is called as T- states. A instruction cycle or machine cycle can take more than one clock periods.

The execution of instruction is generally the execution of the machine cycles of that instruction in the already defined order.
The timing cycle of an instruction can be best understood by obtaining timing diagrams of the machine cycles of that instruction, one by one in the order of execution.
Categories of Machine Cycle :
Machine cycles are categorised on the following basis:

  • On the basis of status signals (IO/M’,S1 and S0 ).
  • On the basis of (RD’,WR’,INTA ).

8085 microprocessor has five basic machine cycles which are as follows:

  • Opcode fetch cycle (4T)
  • Memory Read cycle (3T)
  • Memory Write cycle (3T)
  • I/O Read  cycle (3T)
  • I/O Write cycle (3T)

Now let us explain some of these:
Opcode Fetch Cycle 

  • The opcode fetch cycle fetches the instruction from memory and delivers it to the instruction register of the microprocessor.
  • It is the first machine cycle for any instruction.
  • The opcodes are stored in memory. So the processor executes the opcode fetch machine to fetch the opcode from memory.
  • The time required by the processor to execute the operand fetch cycle is 4T.
  • In this time, the first, 3T states are used for fetching the opcode from memory and the remaining T-states are used for decoding the fetched opcode from the memory.

Various T-states of Opcode fetch cycle are explained as follows:
T1 state :
During this state , the contents of the PC is placed on the 16 bit address bus , in which lower order 8-bits are transferred to multiplexed A/D (AD0-AD7) bus and higher order 8-bita are transferred to the address bus (A8-A15).
After the address bits are transferred, the ALE signal goes high . As soon as ALE goes high, the memory latches the AD0-AD7 bus. In the middle of the T-state the ALE goes low and the complete 16 bit address is made available for the opcode fetch machine cycle.
T2 State :
At the starting of this state, the read signal goes low to enable memory. It is during this state, the selected memory location is placed on D0-D7 of the Address/Data multiplexed bus.
T3 State :
At the beginning of this state the Opcode is already placed on D0-D7 of the A/D bus. During this state of the cycle, the opcode of the A/D bus is transferred to the instruction register of the microprocessor. Now the RD’ goes high after this action and thus disables the memory from A/D bus.
T4 State :
In this state the opcode which was fetched from the memory is decoded.
Thus the opcode which was fetched from the memory is decoded.
Thus the opcode fetch cycle completes after the execution of the 4T-states.
It can be well understood from the above diagram.
Memory Read Machine Cycle of 8085 :
 
This machine cycle is executed to read a data byte from memory. The processor takes 3T states to execute this cycle .The word size will use the machine cycle after the opcode fetch machine cycle.
For example: MVI D, 24H
In the above example, two machine cycles involved . One is the Opcode fetch cycle and the second is the memory read cycle which transfers the operand 24H from the memory to the microprocessor.
T1 State :  
During this state , the content of the PC is placed on the higher order address bus (A8-A15) and lower address and data are multiplexed (AD0-AD7) bus .
The microprocessor identifies the memory read machine cycle from the status signal IO/M’=0 , S1=1 , S0=0. This condition indicates the memory read cycle.
T2 State :
Selected memory location is placed on the (D0-D7) of the A/D multiplexed bus.
T3 State :
The already loaded data is transferred to the microprocessor. In the middle of the T3 state RD’ goes high and disables the memory read operation. The data which was obtained from the memory is then decoded.
This concept of memory read machine cycle can be best understood by above diagram.
I/O Read Machine Cycle :
 
The machine cycle for I/O read machine cycle is almost same as read machine cycle. It is a two byte I/O read instruction.
The first cycle is same i.e. the opcode fetch cycle. The T2 cycle is the I/O read machine cycle, where the content of port address is transferred to the microprocessor.
The status signal for the I/O read machine cycle is different. The status signal values are IO/M’=1, S1= 1, S0=0 .
The concept of I/O Machine cycle can be better understood with the aid of the diagram shown above.