The philosophy behind processor architecture design is that, hardware is always faster than software, which means if user enters the command then latency should be high or get response as soon as possible. To full fill this requirement RISC and CISC architecture designs are used. Therefore processors are designed on two criterias first on the hardware and second on the software so CISC follow complex instruction set computer and RISC follow reduce instruction set computer architecture

Concept behind RISC and CISC architectures

As and when new evolving needs emerge with respect to the hardware design/architecture, hardware architects invent various technologies and tools to implement the desired architecture in order to fulfill these needs. Hardware architecture may be implemented to be either hardware specific or software specific, but according to the application both are used in required proportion. As far as the processor hardware is concerned, there are two types of concepts to implement the processor hardware architecture. First one is Reduce instruction set computer (RISC) and other  one is Complex instruction set computer (CISC)

Intel supporters implement CISC architecture so they provide that software implementation is easy. So the hardware designing is more complex but software coding would be relatively easy. On the other hand, Apple supporters want the hardware to be simple and easy and software to take the major role. Therefore they implement RISC based architecture.

RISC Architecture

RISC architecture based computer provide the minimum set of instructions that can handle all essential operations and instructions complexity is reduced by

  • Having few simple instructions that are of same length and execute in single clock in RISC
  • Allow memory access only with explicit load and store instructions

Hence each instruction takes less time to complete work but execution time is different.

RISC Architecture with watermark

Figure – RISC Architecture

Examples: – Atmel AVR, Apple, LC3, MIPS, PowerPC (IBM), SPARC (Sun)

CISC Architecture

          CISC architecture based computer are designed to reduce the cost of memory because the bigger programs requires more storage thus increasing the cost of memory and large memory becomes more expensive. To solve these problems, the number of instructions per program can be reduced by embedding multiple operations within a single instruction, thereby making instructions more complex.

CISC Architecture with watermark

Figure – CISC Architecture

Example: – 8085, Intel x86 and AMD processor

Difference between RISC and CISC Architecture




Full form

Complex instruction set computer Reduced instruction set computer


Large set of instruction with variable format (16-64 bits/ inst-ruction) Small set of instruction with fixed format (32 bits/instruction)

Complexity of software

Complexity of software in CISC is very high because it has large instruction set. Complexity of software in RISC is very LOW because it has small instruction set.

Complexity of processor

Complexity of processor in CISC is very low because it uses less general purpose registers. Complexity of processor in RISC is very high because it uses more general purpose registers.

Addressing mode

CISC have 12-24 addressing modes RISC have 3-5 addressing modes

General purpose register

CISC have 8-24 General purpose registers RISC have 32-192 General purpose registers

Cache design

Unified cache used for instruction and data Split cache used for instruction and data

Code Size

Small Code Sizes. Large Code Sizes.

Clock rate

CISC have 33-55MHZ clock rate, Instruction execute in multi-clock cycle RISC have 50-150MHZ clock rate, Instruction execute in single clock cycle


No pipelining used by CISC processors Pipelining is used by RISC processor.

CPU control

Most micro coded using control memory (ROM), but modern CISC also uses hardwired control. Most hardwired without control memory


More expensive  Less expensive


Intel 8085,80×86, VAX 8600 Processor, Motorola680040 Processor. Atmel AVR, MICHROCHIP 16F XX Series, I860 Processor, CY7C601 Processor.