An interrupt is a signal generated by an external device that prompts a microprocessor to perform a task. There are 5 interrupt signals, TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
Interrupts are subdivided according to their parameters into the following groups:

  1. Vector Interrupt – In this type of interrupt, the processor knows the interrupt address. For example: RST7.5, RST6.5, RST5.5, TRAP.
  2. Non-Vectorized Interrupts – In this type of interrupt, the processor does not know the interrupt address. The interrupt address must be sent externally by the device to perform the interrupt. For example: INTR.
  3. Mask Interrupts – In this type of interrupt, you can disable interrupts by writing instructions to the program. For example: RST7.5, RST6.5, RST5.5.
  4. Non-Maskable Interrupts – In this type of interrupt, interrupts can not be disabled by writing instructions to the program. For example: TRAP.
  5. Software Interrupt – In this type of interrupt, the programmer must add instructions to the program to execute the interrupt. In the 8085 there are 8 software interrupts, namely RST0, RST1, RST2, RST3, RST4, RST5, RST6 and RST7.
  6. Hardware Interrupts – In 8085, there are five interrupt interrupts for hardware interrupts, TRAP, RST7.5, RST6.5, RST5.5, INTA.

Note – NTA is not an interrupt and the microprocessor uses it to send a confirmation. TRAP has the highest priority, then RST7.5, etc.

Interruption Service Program (ISR)

For a small program or routine, the corresponding interrupt source service is called ISR.

TRAP

This is an unmaskable interrupt with the highest priority among all interrupts. By default, it is enabled until confirmed. If an error occurs, it will be executed as an ISR and the data will be sent to the backup storage. This interrupt transfers the control to position 0024H.

RST7.5

It is a maskable interrupt with the second highest priority among all interrupts. When the interrupt is executed, the processor stores the contents of the PC register in the stack and transfers it to the address 003CH.

RST 6.5

It is a maskable interrupt with the third highest priority of all interrupts. When this interrupt is executed, the processor saves the contents of the PC register in the stack and proceeds to address 0034H.

RST 5.5

It is a maskable interruption. When the interrupt is executed, the processor stores the contents of the PC register in the stack and transfers it to the address 002CH.

INTR

This is a maskable trap with the lowest priority among all interrupts. It can be deactivated by resetting the microprocessor.

When the INTR signal goes high, the following events may occur:

  • The microprocessor checks the status of the INTR signal during the execution of each instruction.
  • When the INTR signal is high, the microprocessor ends the current command and sends an alarm acknowledge signal for a low alarm.
  • When an instruction is received, the microprocessor records the address of the next instruction on the stack and executes the instruction received.