Intel 8255A – Programmable Peripheral Interface Pin Diagram shown in the figure below
Intel 8255A – Programmable Peripheral Interface Pin Diagram
Now let’s discuss the function description of the pins in the 8255A.
It is a tri-state 8-bit buffer that connects the microprocessor to the system data bus. Data is transferred or received from the buffer according to instructions from the CPU. Control words and status information are also transmitted over the bus.
Read / Write control logic
This block is responsible for controlling the internal / external transfer of data / control / status words. It accepts input from the CPU address and the control bus and then issues commands to both control groups.
It stands for Chip Select. The low level of this input selects the chip and allows communication between the 8255A and the CPU. It is connected to the decode address, and A0 and A1 are connected to the address line of the microprocessor.
Their results depend on the following conditions:
It stands for writing. This control signal enables the writing process. When this signal goes low, the microprocessor writes to the selected I / O port or control register.
This is an effective high signal. It clears the control registers and puts all ports in input mode.
It is about reading. This control signal enables the reading process. When the signal is low, the microprocessor reads data from the selected I / O port of the 8255.
A0 and A1
These input signals operate with RD, WR and one of the control signals. The following table shows the different signals and their results.
PORT A → Data Bus
|0||1||0||1||0||PORT B → Data Bus|
|1||0||0||1||0||PORT C → Data Bus|
Data Bus → PORT A
|0||1||1||0||0||Data Bus → PORT A|
|1||0||1||0||0||Data Bus → PORT B|
|1||1||1||0||0||Data Bus → PORT D|