EdITS WORLD Uncategorized Intel 8253 – Programmable Interval Timer

Intel 8253 – Programmable Interval Timer

Intel 8253 – Programmable Interval Timer

The Intel 8253 and 8254 processors are programmable interval programmers (PTIs) designed for microprocessors to perform timing and counting functions using three 16-bit registers. Each register has 2 input pins. For example, clock IN  and 1 pin for the output “OUT”. To operate a counter, a 16-bit counter is loaded into its register. On command, the counter starts to go down to 0 and then generates a pulse that can be used to interrupt the CPU.

Difference between 8253 and 8254

The following table distinguishes the features of 8253 and 8254:

8253 8254
The operating frequency is between 0 and 2.6 MHz. The operating frequency between 0 and 10 MHz.
Uses N-MOS technology. Uses H-MOS technology.
The readback command is not available. The readback command is available.
Reads and writes from the same counter can not be interspersed. Reads and writes from the same counter can be inserted.

Features of 8253/54

  • The main features of 8253/54 are:
  • It has three independent 16-bit counters.
  • It can handle inputs ranging from DC to 10 MHz.
  • These three counters can be programmed for a binary count or BCD.
  • It is compatible with almost all microprocessors.
  • The 8254 has a powerful command called the READ BACK command that allows the user to check the number, programmed mode, current mode, and current counter status.

8254 Architecture or Block Diagram

8253 Pin Diagram

Here is the 8254 game scheme –

8254 Description

In the figure of 8253 block diagram there are three counters, a data buffer, a read / write control logic and a control register. Each counter has two input signals: CLOCK and GATE and one output – OUT.

Data Bus

It is an eight-state bi-directional three-state buffer that acts as an interface between the 8253/54 and the system library. It has three basic functions –

  • Programming mode 8253/54.
  • The counting registers are loaded.
  • Read the values ​​of the count

Read / write logic

It includes 5 signals, namely RD, WR, CS and the address lines AO and Al. In peripheral I / O mode, the RD and WR signals are connected respectively to IOR and IOW. In an I / O mode assigned in memory, they are connected to MEMR and MEMW.

The address lines A0 and A1 of the CPU are connected to lines A0 and A1 of 8253/54 and CS is connected to a decoded address. The control word register and the counters are selected based on the signals of the A0 and A1 lines.

A1 A0 Result
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
X X No selection

Register of passwords

This register is accessible if the A0 and A1 lines are at the logical level. It is used to write a command word that indicates the counter to use, the mode and a read or write operation. The following table shows the result for different control inputs.

A1 A0 RD WR CS Result
0 0 1 0 0 Write Counter 0
0 1 1 0 0 Write Counter 1
1 0 1 0 0 Write Counter 2
1 1 1 0 0 Write Counter Word
0 0 0 1 0 Read Counter 0
0 1 0 1 0 Read Counter 1
1 0 0 1 0 Read Counter 2
1 1 0 1 0 No operation
X X 1 1 1 No operation
X X X X 1 No operation

counter

Each counter consists of a single counter (16 bits less) that can be used in binary or BCD mode. The input and output are configured by selecting the modes stored in the control word register. The programmer can read the contents of one of the three counters without disturbing the current countdown. The 8253/54 can be used in 6 different modes. We discuss these operating modes in this chapter.

Mode 0 – termination at the terminal

  • It is used to generate a microprocessor interrupt after a certain interval.
  • Initially, the output is low after setting the mode. The output remains LOW when the counter is loaded into the counter.
  • The countdown process continues until the final count is reached, that is, the account becomes zero and the output becomes HIGH and remains high until a new account is reloaded.
  • The GATE signal is high for normal counting. If GATE is not active, the account is suspended and the current account is locked until GATE rises again.

Mode 1 – One Shot programmable

  • It can be used as a monostable multivibrator.
  • The gate input is used as the trigger input in this mode.
  • The output remains high until the account loads and a trigger is applied.

Mode 2 – Speed ​​generator

  • The output is normally high after initialization.
  • When the counter reading becomes zero, another low pulse is generated at the output and the counter is reloaded.

Mode 3 – Rectangular generator

  • This mode is similar to Mode 2, but the output remains low for half the timer period and high for the second half of the time period.

Mode 4 – Software-enabled mode

  • In this mode, the output remains high until the timer is counted to zero. Thereafter, the output will output low pulses and then return to high.
  • The account is locked when the GATE signal becomes LOW.
  • When counting the terminal, the output will go low for one clock cycle and thus HIGH. This low pulse can be used as a flash.

Mode 5 – Hardware Weighted Mode

  • This mode is similar to mode 4, except that the count is triggered by a signal at the gate input, which means that the hardware is activated instead of the activated software.
  • After initialization, the output goes high.
  • When the final count is reached, the output goes low for one clock cycle.
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