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8259 programmable interrupt controller (PIC)

8259 programmable interrupt controller (PIC)

The 8259 is defined as a programmable interrupt controller (PIC). In 8085 and 8086 there are 5 hardware interrupts and 2 hardware interrupts. By connecting to 8259 in a processor, you can increase the interruptions in processing capacity. 8259 combines multiple input inputs with a single output disruption. The interface of a single PIC offers 8 inconvenience inputs of IR0-IR7.

For example, 8085 and 8259 interfaces increase the ability to store 8085 microprocessor storage from 5 to 8 levels of interruption.

Features of PIC 8259 microprocessor –

  • The Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessors.
  • It can be programmed at the level of distraction or disturbance.
  • We may hide the individual pieces from the disruption of the register request.
  • By cascading additional 8259 PICs, we can increase the capacity of an interrupt processing at an interrupt level of 64.
  • The clock is not required.

PIN Diagram 8259

The above diagram shows the 28 pins of the 8259 PIC microprocessor, with Vcc: 5V and ground: Gnd. The other pins used are explained below.

Block Diagram of programmable interrupt controller (PIC) 8259 

The diagram consists of 8 data bus buffer blocks, read / write logic, buffer buffer comparison, control logic, priority resolutionver and 3 registers – ISR, IRR, IMR.

1. Data buffer

This block is used as an intermediary between 8259 and 8085/8086 microprocessor, acting as a buffer. The word instruction is required from the microprocessor 8085 (for example) and it transmits to the control logic of the microprocessor 8259. After choosing to interrupt the microprocessor 8259, it also sends the operation code of the selected interrupts and the subroutine address of the service of disruption of other connected microprocessor. The data buffer consists of 8 bits, shown in block diagram as DO-D7. It indicates that maximum 8 data bits can be sent at the same time.

2. Read / write logic

This block only works if the CS pin value is low (because this pin is active). This block is responsible for data flow based on input RD and WR. Both pins are low-active pins used for reading and writing.

3. Control logic

This is the center of the microprocessor and controls the operation of each block. It has an INTR pin connected to another microprocessor to accept the interrupt request and pin INT at output. If the 8259 is active and the flag of the other interrupt microprocessor is high, this means that the INT output pin value is high, and 8,259 respond to this request upon request of other microprocessor requirements.

4. Disturbing request register (IRR)

It stores all levels of interruptions that require interrupt services.

5. Interruption to Service Registration (ISR)

Sells current level of interruption.

6. Prevention of mask register (IMR)

It stores a level bother to be secretive by storing bit caps at the level of the rotation.

7. Essential resolution

Check all three registers and identify the priority of the interrupts. Interruption with the highest priority is set on the ISR register based on prior distraction. In addition, the level of interruption processed on the IRR is restored.

8. Cascade Buffer

In order to increase the rotation processing capacity, a larger number of pins can be cascaded using cascade buffers. When increasing capacity increases, the CSA lines are used to control multiple interrupt structures.

The SP / EN pin (slave program / buffer activation) is set high and works in master mode, otherwise in slave mode. In non-buffered mode, the SP / EN pin specifies whether 8259 should work as a master or slave. In buffered mode, the SP / EN pin is used as an output to enable data bus.

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